Xilinx vivado zynq pldma PL part ILA debugging

Through the previous PL DMA design, running in the SDK, it is normal to not run (block design and source desing are their own hands, obvious errors have been corrected, can generate bit files to start SDK debugging).

xilinx vivado zynq pldma PL部分ILA调试

First debug in the PL section, as the PL DMA control APB bus, set it to Mark Debug, as shown below.

Xilinx vivado zynq pldma PL part ILA debugging

Then re-synthesis, comprehensive completion, do not perform implemenTIon, find "Set Up Debug" under the integrated menu, perform ILA configuration, and the setting window of the following figure appears.

Xilinx vivado zynq pldma PL part ILA debugging

Click “more info” in the above figure, a prompt appears, and some netlists do not have a clock set.

Xilinx vivado zynq pldma PL part ILA debugging

Select all, then right click to select the clock, as shown below

Xilinx vivado zynq pldma PL part ILA debugging

The FCLK_CLK1 clock is selected because this clock is 150Mhz, and the APB bus clock is 50Mhz for FCLK_CLK0, which is easily sampled with a 150Mhz clock and then completed by default. Then generate a bit file.

Debugging process

First start the test program of the PL DMA PS part in the SDK and stop at the main function.

Then in the vivado program device, start the ILA debug window.

Xilinx vivado zynq pldma PL part ILA debugging

Select “Trigger Setup” and the “Trigger Setup” window will appear for the trigger condition setting.

Xilinx vivado zynq pldma PL part ILA debugging

In the above figure, you can add multiple monitoring signals with “+” and set the trigger condition by the following Compare Value. When there are multiple trigger conditions, you can set their trigger relationship by the left logical symbol.

Xilinx vivado zynq pldma PL part ILA debugging

Select the trigger in the above image

Then run the test test under the SDK. After reading the address space corresponding to the APB bus, the debug window information shown in the figure below appears.

Xilinx vivado zynq pldma PL part ILA debugging

The data of the APB bus is normal from the comparison between the data in the figure and the data written in the PS section.

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